`ifndef _ral_reg_REG_PRJ_sys_cfg_cal_config_rtl_
`define _ral_reg_REG_PRJ_sys_cfg_cal_config_rtl_

`include "vmm_ral_rw_field_rtl.sv"
`include "vmm_ral_notifier_rtl.sv"


module ral_reg_REG_PRJ_sys_cfg_cal_config_rtl(input  clk,
                              input  rstn,
                              input  [31:0] hst_wdat,
                              output [31:0] hst_rdat,
                              input  [3:0] hst_sel,
                              input  hst_wen,
                              output [2:0] cal_mode_out,
                              output cal_mode_rd, cal_mode_wr,
                              input  cal_mode_wen,
                              input  [2:0] cal_mode_in,
                              output [2:0] cal_round_out,
                              output cal_round_rd, cal_round_wr,
                              input  cal_round_wen,
                              input  [2:0] cal_round_in,
                              output [2:0] cvt_mode_out,
                              output cvt_mode_rd, cvt_mode_wr,
                              input  cvt_mode_wen,
                              input  [2:0] cvt_mode_in);

vmm_ral_rw_field_rtl #(3, 'h6)
   cal_mode(clk, rstn, cal_mode_out,
   hst_wdat[2:0], hst_sel[0], hst_wen,
   cal_mode_in, cal_mode_wen);

vmm_ral_rw_field_rtl #(3, 'h0)
   cal_round(clk, rstn, cal_round_out,
   hst_wdat[5:3], hst_sel[0], hst_wen,
   cal_round_in, cal_round_wen);

vmm_ral_rw_field_rtl #(2, ('h0>>0))
   cvt_mode_1_0(clk, rstn, cvt_mode_out[1:0],
   hst_wdat[7:6], hst_sel[0], hst_wen,
   cvt_mode_in[1:0], cvt_mode_wen);

vmm_ral_rw_field_rtl #(1, ('h0>>2))
   cvt_mode_2_2(clk, rstn, cvt_mode_out[2:2],
   hst_wdat[8:8], hst_sel[1], hst_wen,
   cvt_mode_in[2:2], cvt_mode_wen);


vmm_ral_notifier_rtl _n_cal_mode(clk, rstn, hst_sel[0], hst_wen, cal_mode_rd, cal_mode_wr);
vmm_ral_notifier_rtl _n_cal_round(clk, rstn, hst_sel[0], hst_wen, cal_round_rd, cal_round_wr);
vmm_ral_notifier_rtl _n_cvt_mode(clk, rstn, |hst_sel[1:0], hst_wen, cvt_mode_rd, cvt_mode_wr);


assign hst_rdat[31:0] = { cvt_mode_out, cal_round_out, cal_mode_out };


endmodule

`endif
